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features ? floating channel designed for bootstrap operation fully operational to +500v or +600v tolerant to negative transient voltage dv/dt immune ? gate drive supply range from 10 to 20v ? undervoltage lockout for both channels ? 3.3v logic compatible separate logic supply range from 3.3v to 20v logic and power ground 5v of fset ? cmos schmitt-triggered inputs with pull-down ? cycle by cycle edge-triggered shutdown logic ? matched propagation delay for both channels ? outputs in phase with inputs ? also available lead-free data sheet no. pd60147 rev. t high and low side driver product summary v offset (ir2110) 500v max. (ir2113) 600v max. i o +/- 2a / 2a v out 10 - 20v t on/off (typ.) 120 & 94 ns delay matching (ir2110) 10 ns max. (ir2113) 20ns max. www.irf.com 1 description the ir2110/ir2113 are high voltage, high speed power mosfet and igbt drivers with independent high and low side referenced output channels. proprietary hvic and latch immune cmos technologies enable ruggedized monolithic construction. logic inputs are compat- ible with standard cmos or lsttl output, down to 3.3v logic. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. propaga- tion delays are matched to simplify use in high frequency applications. the floating channel can be used to drive an n-channel power mosfet or igbt in the high side configuration which operates up to 500 or 600 volts. ir2110( s )/ir2113( s) & (pbf ) hin up to 500v or 600v to load v dd v b v s ho lo com hin lin v ss sd v cc lin v dd sd v ss v cc (refer to lead assignments for correct pin configuration). this/these diagram(s) show electrical connections only. please refer to our application notes and designtips for proper circuit board layout. typical connection packages 14-lead pdip ir2110/ir2113 16-lead soic ir2110s/ir2113s
2 www.irf.com ir2110( s )/ir2113(s) & ( pbf) recommended operating conditions the input/output logic timing diagram is shown in figure 1. for proper operation the device should be used within the recommended conditions. the v s and v ss offset ratings are tested with all supplies biased at 15v differential. typical ratings at other bias conditions are shown in figures 36 and 37. note 1: logic operational for v s of -4 to +500v. logic state held for v s of -4v to -v bs . (please refer to the design tip dt97-3 for more details). note 2: when v dd < 5v, the minimum v ss offset is limited to -v dd. absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. additional information is shown in figures 28 through 35. symbol definition min. max. units v b high side floating supply voltage (ir2110) -0.3 525 (ir2113) -0.3 625 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side fixed supply voltage -0.3 25 v lo low side output voltage -0.3 v cc + 0.3 v dd logic supply voltage -0.3 v ss + 25 v ss logic supply offset voltage v cc - 25 v cc + 0.3 v in logic input voltage (hin, lin & sd) v ss - 0.3 v dd + 0.3 dv s /dt allowable offset supply voltage transient (figure 2) ? 50 v/ns p d package power dissipation @ t a +25 c (14 lead dip) ? 1.6 (16 lead soic) ? 1.25 r thja thermal resistance, junction to ambient (14 lead dip) ? 75 (16 lead soic) ? 100 t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 c/w w v c symbol definition min. max. units v b high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage (ir2110) note 1 500 (ir2113) note 1 600 v ho high side floating output voltage v s v b v cc low side fixed supply voltage 10 20 v lo low side output voltage 0 v cc v dd logic supply voltage v ss + 3 v ss + 20 v ss logic supply offset voltage -5 (note 2) 5 v in logic input voltage (hin, lin & sd) v ss v dd t a ambient temperature -40 125 c v
www.irf.com 3 ir2110(s)/ir2113(s) & ( pbf) symbol definition figure min. typ. max. units test conditions t on turn-on propagation delay 7 ? 120 150 v s = 0v t off turn-off propagation delay 8 ? 94 125 v s = 500v/600v t sd shutdown propagation delay 9 ? 110 140 v s = 500v/600v t r turn-on rise time 10 ? 25 35 t f turn-off fall time 11 ? 17 25 mt delay matching, hs & ls (ir2110) ? ? ? 10 turn-on/off (ir2113) ? ? ? 20 ns dynamic electrical characteristics v bias (v cc , v bs , v dd ) = 15v, c l = 1000 pf, t a = 25 c and v ss = com unless otherwise specified. the dynamic electrical characteristics are measured using the test circuit shown in figure 3. symbol definition figure min. typ. max. units test conditions v ih logic ?1? input voltage 12 9.5 ? ? v il logic ?0? input voltage 13 ? ? 6.0 v oh high level output voltage, v bias - v o 14 ? ? 1.2 i o = 0a v ol low level output voltage, v o 15 ? ? 0.1 i o = 0a i lk offset supply leakage current 16 ? ? 50 v b =v s = 500v/600v i qbs quiescent v bs supply current 17 ? 125 230 v in = 0v or v dd i qcc quiescent v cc supply current 18 ? 180 340 v in = 0v or v dd i qdd quiescent v dd supply current 19 ? 15 30 v in = 0v or v dd i in+ logic ?1? input bias current 20 ? 20 40 v in = v dd i in- logic ?0? input bias current 21 ? ? 1.0 v in = 0v v bsuv+ v bs supply undervoltage positive going 22 7.5 8.6 9.7 threshold v bsuv- v bs supply undervoltage negative going 23 7.0 8.2 9.4 threshold v ccuv+ v cc supply undervoltage positive going 24 7.4 8.5 9.6 threshold v ccuv- v cc supply undervoltage negative going 25 7.0 8.2 9.4 threshold i o+ output high short circuit pulsed current 26 2.0 2.5 ? v o = 0v, v in = v dd pw 10 s i o- output low short circuit pulsed current 27 2.0 2.5 ? v o = 15v, v in = 0v pw 10 s static electrical characteristics v bias (v cc , v bs , v dd ) = 15v, t a = 25 c and v ss = com unless otherwise specified. the v in , v th and i in parameters are referenced to v ss and are applicable to all three logic input leads: hin, lin and sd. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. v a v a
4 www.irf.com ir2110( s )/ir2113(s) & ( pbf) functional block diagram lead definitions symbol description 14 lead pdip 16 lead soic (wide body) ir2110/ir2113 ir2110s/ ir2113s v b sd lin v dd pulse gen r s q v ss uv detect delay hv level shift v cc pulse filter uv detect v dd /v cc level shift v dd /v cc level shift lo v s com r s q r s rq hin ho v dd logic supply hin logic input for high side gate driver output (ho), in phase sd logic input for shutdown lin logic input for low side gate driver output (lo), in phase v ss logic ground v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side supply lo low side gate drive output com low side return lead assignments
www.irf.com 5 ir2110(s)/ir2113(s) & ( pbf) figure 1. input/output timing diagram figure 2. floating supply voltage transient test circuit figure 3. switching time test circuit figure 4. switching time waveform definition figure 6. delay matching waveform definitions figure 5. shutdown waveform definitions hin lin t r t on t f t off ho lo 50% 50% 90% 90% 10% 10% hin lin ho 50% 50% 10% lo 90% mt ho lo mt sd t sd ho lo 50% 90% 10 f 0.1 f v =15v cc 9 36 5 7 1 2 13 12 11 10 hin sd lin ho lo 0.1 f 10 f 10 f c l c l v b + - s v (0 to 500v/600v) 15v 10 f 0.1 f v =15v cc 9 36 5 7 1 2 13 12 11 10 ho 0.1 f output monitor 10kf6 10kf6 200 h 10kf6 100 f + irf820 hv = 10 to 500v/600v dv s >50 v/ns dt
6 www.irf.com ir2110( s )/ir2113(s) & ( pbf) figure 8a. turn-off time vs. temperature figure 7a. turn-on time vs. temperature figure 7b. turn-on time vs. v cc /v bs supply voltage 0 50 100 150 200 250 10 12 14 16 18 20 turn-on delay time (ns) max. typ. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature (c) turn-on delay time (ns) max. typ. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature (c) turn-off delay time (ns) max. typ. 0 50 100 150 200 250 0 2 4 6 8 101214161820 ma x . ty p . figure 7c. turn-on time vs. vdd supply voltage figure 8b. turn-off time vs. v cc /v bs supply voltage 0 50 100 150 200 250 10 12 14 16 18 20 turn-off delay time (ns) max. typ. 0 50 100 150 200 250 0246810121416182 0 ma x . ty p figure 8c. turn-off time vs. v dd supply voltage v dd supply voltage (v) turn-on delay time (ns) v cc /v bs supply voltage (v) v cc /v bs supply voltage (v) v dd supply voltage (v) turn-off delay time (ns)
www.irf.com 7 ir2110(s)/ir2113(s) & ( pbf) figure 9b. shutdown time vs. v cc /v bs supply voltage figure 9a. shutdown time vs. temperature 0 50 100 150 200 250 10 12 14 16 18 20 shutdown delay time (ns) max. typ. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature (c) shutdown delay time (ns) max. typ. 0 50 100 150 200 250 02468101214161820 vdd supply voltage (v) max . t yp shutdown delay time (ns) figure 9c. shutdown time vs. v dd supply voltage figure 10a. turn-on rise time vs. temperature 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature (c) turn-on rise time (ns) max. typ. figure 10b. turn-on rise time vs. voltage 0 20 40 60 80 100 10 12 14 16 18 20 v bias supply voltage (v) turn-on rise time (ns) max. typ. figure 11a. turn-off fall time vs. temperature 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 temperature (c) turn-off fall time (ns) max. typ. v cc /v bs supply voltage (v)
8 www.irf.com ir2110( s )/ir2113(s) & ( pbf) figure 11b. turn-off fall time vs. voltage 0 10 20 30 40 50 10 12 14 16 18 20 v bias supply voltage (v) turn-off fall time (ns) max. typ. figure 12a. logic ?1? input threshold vs. temperature 0.0 3.0 6.0 9.0 12.0 15.0 -50 -25 0 25 50 75 100 125 temperature (c) logic "1" input threshold (v) min. max figure 12b. logic ?1? input threshold vs. voltage figure 13a. logic ?0? input threshold vs. temperature 0.0 3.0 6.0 9.0 12.0 15.0 -50 -25 0 25 50 75 100 125 temperature (c) logic "0" input threshold (v) max. min. figure 13b. logic ?0? input threshold vs. voltage figure 14a. high level output vs. temperature 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) high level output voltage (v) max. logic " 1" input threshold (v) 0 3 6 9 12 15 0 2 4 6 8 10 12 14 16 18 20 max. v dd logic supply voltage (v) 0 3 6 9 12 15 02468101214161820 min . logic "0" input threshold (v) v dd logic supply voltage (v)
www.irf.com 9 ir2110(s)/ir2113(s) & ( pbf) figure 14b. high level output vs. voltage 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 v bias supply voltage (v) high level output voltage (v) m ax. figure 15a. low level output vs. temperature 0.00 0.20 0.40 0.60 0.80 1.00 -50 -25 0 25 50 75 100 125 temperature (c) low level output voltage (v) max. figure 15b. low level output vs. voltage 0.00 0.20 0.40 0.60 0.80 1.00 10 12 14 16 18 20 v bias supply voltage (v) low level output voltage (v) m ax. figure 16a. offset supply current vs. temperature 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature (c) offset supply leakage current (a) max. figure 16b. offset supply current vs. voltage 0 100 200 300 400 500 0 100 200 300 400 500 600 v b boost voltage (v) offset supply leakage current (a) max. ir2110 ir2113 figure 17a. v bs supply current vs. temperature 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature (c) v bs supply current (a) max. typ.
10 www.irf.com ir2110( s )/ir2113(s) & ( pbf) figure 19b. v dd supply current vs. v dd voltage figure 20a. logic ?1? input current vs. temperature 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature (c) logic "1" input bias current (a) max. typ. figure 17b. v bs supply current vs. voltage 0 100 200 300 400 500 10 12 14 16 18 20 v bs floating supply voltage (v) v bs supply current (a) max. typ. figure 18a. v cc supply current vs. temperature 0 125 250 375 500 625 -50 -25 0 25 50 75 100 125 temperature (c) v cc supply current (a) max. typ. figure 18b. v cc supply current vs. voltage 0 125 250 375 500 625 10 12 14 16 18 20 v cc fixed supply voltage (v) v cc supply current (a) max. typ. figure 19a. v dd supply current vs. temperature 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature (c) v dd supply current (a) max. typ. 0 10 20 30 40 50 60 02468101214161820 v dd supply current ( a) v dd logic supply voltage (v)
www.irf.com 11 ir2110(s)/ir2113(s) & ( pbf) figure 21a. logic ?0? input current vs. temperature figure 21b. logic ?0? input current vs. v dd voltage figure 20b. logic ?1? input current vs. v dd voltage 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) logic "0" input bias current (a) max. 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v bs undervoltage lockout + (v) max. typ. min. figure 22. v bs undervoltage (+) vs. temperature figure 23. v bs undervoltage (-) vs. temperature 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v bs undervoltage lockout - (v) max. typ. min. 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v cc undervoltage lockout + (v) max. typ. min. figure 24. v cc undervoltage (+) vs. temperature logic ?1? input bias current ( a) v dd logic supply voltage (v) 0 10 20 30 40 50 60 02468101214161820 logic ?0? input bias current ( a) v dd logic supply voltage (v) 0 1 2 3 4 5 02468101214161820
12 www.irf.com ir2110( s )/ir2113(s) & ( pbf) figure 26b. output source current vs. voltage 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 v bias supply voltage (v) output source current (a) min. typ. figure 27a. output sink current vs. temperature 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) output sink current (a) min. typ. figure 27b. output sink current vs. voltage 0.00 1.00 2.00 3.00 4.00 5.00 10 12 14 16 18 20 v bias supply voltage (v) output sink current (a) min. typ. figure 28. ir2110/ir2113 t j vs. frequency (irfbc20) r gate = 33 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v figure 25. v cc undervoltage (-) vs. temperature 6.0 7.0 8.0 9.0 10.0 11.0 -50 -25 0 25 50 75 100 125 temperature (c) v cc undervoltage lockout - (v) max. typ. min. figure 26a. output source current vs. temperature 0.00 1.00 2.00 3.00 4.00 5.00 -50 -25 0 25 50 75 100 125 temperature (c) output source current (a) min. typ.
www.irf.com 13 ir2110(s)/ir2113(s) & ( pbf) figure 29. ir2110/it2113 t j vs. frequency (irfbc30) r gate = 22 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v figure 30. ir2110/ir2113 t j vs. frequency (irfbc40) r gate = 15 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v figure 31. ir2110/ir2113 t j vs. frequency (irfpe50) r gate = 10 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v figure 32. ir2110s/ir2113s t j vs. frequency (irfbc20) r gate = 33 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v figure 33. ir2110s/ir2113s t j vs. frequency (irfbc30) r gate = 22 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v figure 34. ir2110s/ir2113s t j vs. frequency (irfbc40) r gate = 15 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v
14 www.irf.com ir2110( s )/ir2113(s) & ( pbf) figure 35. ir2110s/ir2113s t j vs. frequency (irfpe50) r gate = 10 ? ? ? ? ? , v cc = 15v 0 25 50 75 100 125 150 1e+2 1e+3 1e+4 1e+5 1e+6 frequency (hz) junction temperature (c) 320v 140v 10v figure 36. maximum v s negative offset vs. v bs supply voltage -10.0 -8.0 -6.0 -4.0 -2.0 0.0 10 12 14 16 18 20 v bs floating supply voltage (v) v s offset supply voltage (v) typ. figure 37. maximum v ss positive offset vs. v cc supply voltage 0.0 4.0 8.0 12.0 16.0 20.0 10 12 14 16 18 20 v cc fixed supply voltage (v) v ss logic supply offset voltage (v) typ.
www.irf.com 15 ir2110(s)/ir2113(s) & ( pbf) 01-6010 01-3002 03 (ms-001ac) 14-lead pdip 16-lead soic (wide body) 01 6015 01-3014 03 (ms-013aa) case outlines
16 www.irf.com ir2110( s )/ir2113(s) & ( pbf) leadfree part marking information order information basic part (non-lead free) 14-lead pdip ir2110 order ir2110 14-lead pdip ir2113 order ir2113 16-lead soic ir2110s order ir2110s 16-lead soic ir2113s order ir2113s leadfree part 14-lead pdip ir2110 order ir2110pbf 14-lead pdip ir2113 order ir2113pbf 16-lead soic ir2110s order ir2110spbf 16-lead soic ir2113s order ir2113spbf lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 this product has been qualified per industrial level data and specifications subject to change without notice. 4/2/2004

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